Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks

Abstract

Chip Multiprocessors(CMPs) and Multiprocessor System-on-Chips(MPSoCs) are meeting the ever increasing demand for high performance in processing large scale data and applications. There is a corresponding increase in the volume and frequency of traffic in the Network-on-Chip(NoC) architectures like CMPs and SoCs. NoC performance parameters like network latency, flit latency and hop count are critical measures which directly influence the overall performance of the architecture and execution time of the application. Unfortunately, cycle-accurate software simulators become slow for interactive use with an increase in architectural size of NoC. In order to provide the chip designer with an efficient framework for accurate measurements of NoC performance parameters, we propose a Machine Learning(ML) framework. Which is designed using different ML regression algorithms like Support Vector Regression(SVR) with different kernels and Artificial Neural Networks(ANN) with different activation functions. The proposed learning framework can be used to analyze the performance parameters of Mesh and Torus based NoC architectures. Results obtained are compared against the widely used cycle-accurate Booksim simulator. Experiments were conducted by variables like topology size from $2\times 2$ to $30\times 30$ with different virtual channels, traffic patterns and injection rates. The framework showed an approximate prediction error of 5% to 8% and overall minimum speedup of $1500\times$ to $2000\times$ .