LUT’s Sliding Backup

Abstract

Reliability is one of the most important quality indicators of hardware (and software of course), including field-programmable gate array (FPGA). Fault-tolerant systems (FTSs) use structural, temporal, or information redundancy to ensure the reliability. Passive FTS due to very large redundancy (modular redundancy) produces fault masking. Active FTSs have less redundancy, but require comparatively more diagnostic and reconfiguration time to switch out faulty elements and to switch in spare elements. The author proposes sliding backup (SR) logic for the high reliability FPGA. The capabilities of SR provide modern FPGAs. It is only necessary to ensure the possibility of prompt reconfiguration of all or part of the FPGA and such capabilities are already provided by some manufacturers. This paper focuses on proposed fault Look up Tables (LUTs) scaling, simulation of the self-checked LUT, and fast reverse testing. Evaluations confirm high efficiency of the proposed method.