<title>Wavelet application programmer's interface for the TriMedia</title>

Abstract

A wavelet Application Programmers' Interface (API) for the TriMedia TM1000 multimedia processor will be described and demonstrated. The challenge undertaken for this API was to provide a single scalable interface to a subband encoder with acceptable performance at bit rates from 9600 bps to 2 Mbps. Further, the API as designed supports the utilization of multiple TriMedia resources. Specifically, the encoder to be demonstrated, is a fully motion compensated wavelet transform which does not utilize the Discrete Cosine Transform (DCT) for the encoding of the prediction errors. The video encoder has numerous novel features including: an integer valued limited precision wavelet transform; a fully motion compensated wavelet API; integral support for multiple processors; and simple mapping to hardware. The integer valued wavelet transform being demonstrated fits into a general class of processing methods. This facilitates the calculation of wavelet transforms in limited precision arithmetic. Specifically, the transform to be described permits the calculation of 25 subbands from 8 bit data with a 16 bit word length. Details of the loading on the Philips TriMedia will be provided including the utilization of the instruction pipeline for the inner loops of the wavelet transform. The API includes a fully motion compensated wavelet transform which greatly improves the visual quality and achievable frame rate over low bit rate channels. One unique feature of the motion compensation (again, patent pending) is that the interframe coding does not require the use of the DCT, which greatly simplifies the implementation of the motion prediction. We will demonstrate the gains achievable with and without motion compensation in the real time encoding and encoding of video sequences. How the API maps across multiple processors will also be demonstrated and a sample application for high field rate with broadcast quality will be presented. The demonstration program control flow will be provided and system performance presented. Finally, the above wavelet encoder is being mapped to both low cost Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) and the resulting implementations and performance, including gate count and required pixel rates, outlined.