<title>Special architecture for edge detection using the residue number system</title>

Abstract

This paper describes a special architecture which detects edges of an image using the Laplacian of Gaussian (LOG) operator. Since edge detection with the LOG operator is a computation bound problem, the special architecture is designed to do parallel processing. The parallel processing is achieved by using the residue number system (RNS) and the systolic concept. The special architecture consists of an output converter, which converts the residue number to the binary number, and eight processing elements, one for each modular number. Both processing elements and output converter are designed as a systolic array. The 2 micrometers CMOS technology is used to layout the basic logic gates. Using the delay times of these gates, the special architecture is simulated with Verilog-XL. As a result of simulation, a 50 MHz clock is selected as the system clock, which is fast enough to detect edges of an image frame in a TV frame time. Hence, the special architecture can be applied to the real-time vision system.