Abstract
Power consumption regularities of the most perspective quasi-adiabatic base logic gates are investigated by method of computer modeling. The effect of abnormal high power consumption in a range of low frequencies is discovered and explained; the method of its neutralization is offered. It is revealed, that in a range of high frequencies energy dissipation in gates decreases at reduction of clock frequency more poorly, than under the law 1 / <i>f</i> . The mechanism of this anomaly is found out. The established laws a power consumption of the base logic gates allow to choose the compromise between power consumption and speed, optimize power characteristics of base gates. It's also allowed to predict their improvement at quality improvement of technology.
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