<title>Parallel implementation of some fast adaptive algorithms on a digital signal processor network</title>

Abstract

Several important problems in signal processing, such as linear prediction, linear regression, or spectrum factorization, need close-to-Toeplitz matrices to be factored. To solve these problems, several fast algorithms have been derived. They differ by the kind of adaptivity (block processing or exponential weighting of the data) and by the kind of recursion (order or time recursion), but they all have a common vector ladder recursion, involving an hyperbolic rotation. These algorithms are therefore well suited for implementation on an array processor. But there exists a number of applications where an efficient parallel implementation of these algorithms on a DSP network would be very attractive. The redundancy suppression, which is performed in the equations to get a fast algorithm, destroys the processing regularity of the corresponding standard algorithms, which prevents efficient high level parallel implementation. Auxiliary quantities, such as generalized reflections coefficients, are introduced that don't have the same dimensions as primary quantities. As a result there is a loss of efficiency in such tasks processing, and this leads to use array partitioning in as many sub-arrays as the number of DSPs available. If the number m of DSPs is low compared to primary quantities of dimension p (m << p/m) (i.e. a low level parallelism) and if the dimension a of reflection coefficients is also low ((alpha) << p/m), the global efficiency of a parallel implementation on a DSP network may still be interesting, with in addition, the advantages associated to such a network : simple design, simple control. To illustrate this, an application of the method to a Fast Recursive Least Squares algorithm is presented.