Abstract
This paper describes a mapping technique for transforming a linear systolic array into multidimensional systolic arrays in order to achieve high-speed with less overhead. This technique is systematic, therefore, it would be useful for logic synthesis. The application of this technique in DSP and numerical computations reduces the design time which results in low design cost. This technique produces various structures (semi-systolic, quasi-systolic and pure systolic arrays) which could be considered as application specific array processors.
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