<title>Flexible MPEG audio decoder core with low power consumption and small gate count</title>

Abstract

In this paper we present the hardware realization of an Audio decoder according to the ISO/IEC 11172-3 (MPEG 1 Audio). The aim of this development was the implementation of a MPEG 1 Audio layer 1/2 decoder core that can be used as a standalone solution as well as in combination with other functionalities (e.g. video-decoder) integrated on one chip. To match these requirements, it is essential to achieve low power consumption and to minimize the demand of chip area. In the described system, optimization was carried out on the algorithmic level as well as on the architectural level. On the algorithmic level, the number of multiplications per audio sample was diminished by about 50% compared to the solution presented in the standard, modifying the necessary polyphase filterbank. On the architectural level, the system exploits parallelism and resource sharing to minimize the number of computation units and the size of memory. The decoding sequence is divided into several processes which run in parallel. In this way, the computation unit can be shared by time multiplex between the different processes and run almost continually. Communication between the processes is realized with shared memory. A technique to minimize the lifetime of data in memory by a kind of virtual addressing is presented. By using these optimization techniques the developed core has a gate count of only about 35 k (including on chip memory) and can be run at a clock rate of 16 MHz which results in a low power consumption.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.