<title>Error detection and correction in an optoelectronic memory system</title>

Abstract

This paper describes the implementation of error detection and correction logic in the optoelectronic cache memory prototype at the University of Pittsburgh. In this project, our goal is to integrate a 3-D optical memory directly into the memory hierarchy of a personal computer. As with any optical storage system, error correction is essential to maintaining acceptable system performance. We have implemented a fully pipelined, real time decoder for 60-bit Spectral Reed-Solomon code words. The decoder is implemented in reconfigurable logic, using a single Xilinx 4000-series FPGA per code word and is fully scalable using multiple FPGA's. The current implementation operates at 33 Mhz, and processes two code words in parallel per clock cycle for an aggregate data rate of 4 Gb/s. We present a brief overview of the project and of Spectral Reed-Solomon codes followed by a description of our implementation and performance data.