<title>Effect of Fe and Cu contamination on the reliability of ultrathin gate oxides</title>

Abstract

The detrimental effect of heavy metal contamination on gate oxide reliability has been well documented for oxides thicker than 7 nm. This study offers evidence of the detrimental effect that metallic (Fe, Cu) contamination has on ultra-thin gate oxide reliability. Oxides grown at 850 degrees Celsius of 3.5 and 7 nm thickness were intentionally contaminated with Fe (pre-oxidation) or Cu (pre- and post-oxidation.) Bulk silicon FE concentrations of 5 X 10<SUP>10</SUP> to 1 X 10<SUP>13</SUP> atoms/cm<SUP>3</SUP> were achieved through the spin doping of an aqueous FeCl<SUB>3</SUB> solution on the wafer surface prior to oxidation. Pre-oxidation Cu contamination was attained through full wafer immersion in a 10:1 HF:H<SUB>2</SUB>O solution contaminated with CuSO<SUB>4</SUB> of varying Cu concentrations (1 ppb to 100 ppb), while post-oxidation contamination results from a 30 minute 450 degree Celsius forming gas anneal which drives in Cu previously deposited on the backside of the wafer. A new corona-based technique was used to measure the stress-induced leakage current (SILC) characteristics of the contaminated and control oxides after various stress fluences, from 10<SUP>-5</SUP> to 10<SUP>-1</SUP> C/cm<SUP>2</SUP>, in either the Fowler-Nordheim or the direct tunneling regime for the 7 and 3.5 nm oxides respectively. This non-contact technique employing the COCOS (Corona Oxide Characterization of Semiconductor) methodology measures current flowing through the oxide as a function of the oxide electric field induced by corona. In addition, electrical measurements on MOS capacitors were performed and the results compared to COCOS SILC results. For the 7 nm oxides, COCOS measurements clearly showed enhanced SILC due to metallic contamination confirming previous findings. For the 3.5 nm oxides, two distinct features were established: (1) pre-stress I-V characteristics were consistent with a direct tunneling mechanism exhibiting a distinct shift to higher currents at lower electric fields and (2) the SILC was smaller in magnitude than that exhibited by the 7 nm oxides. Existing SILC models (i.e. trap-assisted tunneling) were used to interpret the I-V data. In addition, this stress resulted in oxide wearout, which produced noticeable flat-band shifts and an order of magnitude increase in interface state density, also measured using the COCOS technique. The effect of metallic contamination on these wearout issues was also investigated.