<title>Challenges facing 3D information extraction by CD-SEM and scatterometry</title>

Abstract

The accelerated reduction in feature size and the use of Damascene and advanced etching of gate electrodes is greatly challenging critical dimension and defect review metrology. These issues are discussed in the International Technology Roadmap for Semiconductors' Metrology Roadmap. Scanning electron microscopes (SEM) now require 3D imaging and metrology capability and other methods such as scatterometry and CD-AFM provide sidewall angle. Recent evaluation of the depth of field of SEM is below the typically expected micron range. In addition, improving precision, which is directly tied to resolution, can be done only at the expense of either beam voltage or depth of filed field. This greatly limits the application of CD-SEM to sub 70 nm technology generations (logic gates of 45 nm) unless a breakthrough in technology is achieved. Other methods also face challenges. Scatterometry is being extended to provide more than just the typical flat sidewall angle for advanced gate geometries. Metal gates seem to be a tremendous challenge considering that the relative transparency of poly silicon allows scatterometry an advantage. In this paper, the limitations of SEM, scatterometry, and AFM will be discussed in terms of future measurement requirements. An attempt to include new materials, such as porous low k interconnects, in this discussion will also be done.