<I>SCoPE</I>: Statistical Regression Based Power Models for Co-Processors Power Estimation

Abstract

Simulation of a System-on-Chip (SoC) design at register transfer level (RTL) containing various co-processors and logic units is often too time consuming. This poses a problem for power estimation because the best available tools for power estimation today (e.g., PowerTheater) require RTL simulation. Therefore, it is important to obtain abstract power models of the various components that can be utilized at levels higher than the RTL. Availability of such power models can speed up power estimation of the entire chip without resorting to full-chip simulation of the RTL model. However, to be useful, power estimates obtained from such abstract models must be sufficiently accurate. In this paper, we present Statistical regression based Co-processor Power Estimation (SCoPE) methodology, which utilizes cycle accurate Finite State Machine with Datapath (FSMD) models for various co-processors to obtain accurate power estimation. We show through a number of experiments that hardware design implemented on 180 nm technology library show no more than 6% worst-case loss of accuracy, and 9% for 90 nm, with respect to the state-of-the-art RTL power estimation techniques.