Low-voltage Low-power current-mode square-root circuit based on Quasi-floating gate technique

Imen Aloui,Kamel Besbes,Nejib Hassen,Pascal Nouet

doi:10.1109/ssd49366.2020.9364230

Low-voltage Low-power current-mode square-root circuit based on Quasi-floating gate technique

Imen Aloui, Kamel Besbes + Show 2 more

https://doi.org/10.1109/ssd49366.2020.9364230

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Publication Date: Jul 20, 2020

Citations: 3

Affiliation: University of Monastir, University of Sousse, Montpellier Laboratory of Informatics, Robotics and Microelectronics, University of Montpellier, French National Centre for Scientific Research

#Quasi-floating Gate Technique #Μm TSMC Technology + Show 8 more

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Abstract

A high performance low-voltage low-power current-mode square root circuit is presented in this paper. The stacked-up topology with quasi-floating gate MOS translinear loop in subthreshold region is the basic building block of the proposed circuit. Simulation results including Monte Carlo analysis are ascertained through Cadence using 0.18μm TSMC technology under a supply voltage of 0.8V. The simulation results show a lower power consumption (0.145 μW) with respect to literature and a large bandwidth (14 MHz).

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