Abstract
A high performance low-voltage low-power current-mode square root circuit is presented in this paper. The stacked-up topology with quasi-floating gate MOS translinear loop in subthreshold region is the basic building block of the proposed circuit. Simulation results including Monte Carlo analysis are ascertained through Cadence using 0.18μm TSMC technology under a supply voltage of 0.8V. The simulation results show a lower power consumption (0.145 μW) with respect to literature and a large bandwidth (14 MHz).
Published Version
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