Low-voltage low-power CMOS design

Abstract

Minimal power dissipation is one of the main characteristics of portable devices, smart sensor networks and nodes, medical equipments, etc. The best choice is the sub threshold CMOS regime, where supply voltage is lower than threshold voltage of MOS transistor. In this paper it is shown that in sub threshold CMOS regime, dissipation is influenced by transistor threshold voltage, beside supply voltage and CMOS technology parameters. It is shown that by decreasing threshold voltage the total dissipation increases. An energy efficient design means multiple-threshold CMOS. The analytic model of CMOS inverter dissipation is confirmed with simulations of 1-bit adder in P Spice, with implementation of 90 nm CMOS technology parameters.