Low-Voltage, Flexible IGZO Transistors Gated by PSSNa Electrolyte

Abstract

A carving, cutting, and flip-chip bonding process is proposed for the fabrication of flexible electric double layer transistors (EDLTs) with low cost. Solution processed poly(styrenesulfonic acid sodium salt) is used as a gate dielectric. The large EDL-specific capacitance ( $4.5~\mu \text{F}$ /cm2 at 20 Hz) can induce very high charge carrier density in the InGaZnO (IGZO) channel layer, enabling the EDLTs to operate at a single-battery-drivable low voltage of 1.0 V with a high on-current of 10−4A. The effect of IGZO layer thickness on the performance of EDLTs was investigated. The flexible EDLT with optimized IGZO thickness of 100 nm has achieved a high on/off ratio of $1.4 \times 10^{7}$ , a low threshold voltage of 0.51 V, a saturated field-effect mobility of 1.14 cm2/Vs, and high positive gate bias stress stability. Furthermore, the achieved subthreshold swing, 76 mV/dec, is very close to the theoretical ideal minimum value.