Low-Trigger LDMOS-SCR For ESD Protection Of Single Photon Detector

Abstract

In order to improve the anti-ESD capability of the single photon detector core chip, a one-way low-trigger LDMOS-SCR device structure is used for on-chip ESD protection. Based on a 0.5μm standard CMOS process, Analyze the working mechanism of the device through the equivalent circuit and two-dimensional device simulation. The P+ implant region is set on the trigger surface of the LDMOS-SCR to reduce the trigger voltage of the device, and DNW is added to prevent the substrate noise carriers from affecting the device. The results show that the trigger voltage of the low-trigger LDMOS-SCR device is 19.57V, the sustain voltage is 5.37V, the failure current is 7.35A, and the HBM level is 11KV. The test results meet the ESD protection requirements of the single photon detector core chip. By adjusting the size of D6, it is found that the increase of D6 size can effectively improve the sustain voltage of LDMOS-SCR device and effectively prevent latch-up effect. And the failure level of the device will not be significantly reduced.