Abstract
A complete capacitor-over-interconnect (COI) modular ferroelectric random access memory (FeRAM) is demonstrated. A zero switching time transient approach is adopted to extract the HSPICE model files, and a 128-Kb 1T/1C/ 64-Kb 2T/2C dual function test chip is designed. A novel plate line-driven while bit line (BL)-driven operation scheme is used to achieve fast access speed. In order to build the capacitor-over-interconnect (COI) structure, the FeRAM capacitor must be built at <450/spl deg/C. By using a conductive perovskite LaNiO/sub 3/ (LNO) bottom electrode as seed layer, the crystallization temperature of in situ sputter deposited PZT is greatly reduced to 400/spl deg/C/spl sim/450/spl deg/C. This low processing temperature allows the stacking of ferroelectric capacitor on top of CMOS interconnect. The 2Pr value of the low-temperature grown PZT is about 20 /spl mu/C/cm/sup 2/ and provides 130-400 mV of sensing margin even with high BL capacitance of 800 fF.
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