Abstract
INTRODUCTION With the breakdown of Dennard’s scaling rule, chip power for a given area size is not constant as transistors shrink from generation to generation [1]. In particular, the power wall problem worsens with the continual improvement in performance of high-performance computers. The power challenge has been identified as the biggest research challenge [2]. Practical exascale systems of the future should meet a power constraint of 20 MW [2]. The Tianhe-2 system, the fastest supercomputer on the TOP500 list of June 2015, consumes 17.8 MW in running the high-performance Linpack (HPL) benchmark, achieving a performance of 33.86 Pflops. Compared with the Tianhe-2, an exascale system must obtain 30 times the performance improvement with 1.12 times the increase in power consumption. Clearly, in creating such exascale systems, satisfying such power requirements using evolutionary approaches is near impossible. Realizing this challenging power target depends on improvements in many technologies, especially, the viable and revolutionary technologies including new devices, innovative architectures and systems, and energy-aware intelligent technologies; see Figure 1.
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