Abstract
The architectural design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on a multirate algorithm. It can have very low-power dissipation owing to the reduction in hardware complexity and operational frequency. Design application for an IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6 mW when operated at 2 V.
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