Abstract
In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing one to reduce power without performance degradation. As a result of application to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing became less effective. The CVS is considered to be a key technique toward the deep sub-micron age, in which the wire capacitance will be further dominant.
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