Low-Power Array Design Techniques

Abstract

This chapter introduces circuit technologies that enhance electric stability of the cell, the latest technologies that provide moderate timing generation, as well as larger cell stability. In Sect. 5.1, the voltage-adapted timing-generation scheme with plural dummy cells for the wider-voltage-range operation is introduced. The effect of increasing the number of activated dummy cells on the dummy-bitline-driving-time fluctuation is described. Detailed circuit diagrams of the dummy-column cell and edge-column cell are shown. The cache was fabricated using 0. 18 − μm enhanced CMOS technology. The cache chip can continuously operate from 0.65 to 2.0 V; its operating frequency and power are from 120 MHz at 1.7 mW and 0.65 V to 1.04 GHz at 530 mW and 2.0 V. In the next section, read and write stability assisting circuits are discussed. Local variation of transistors is one of the serious issues in sub 100 nm era. This section describes SRAM assist circuits that enhance stability of the cell despite the local variation. Source bias circuit is introduced to enhance the stability in write operation, while word line lowering enhances SNM in read operation. These circuit techniques do not need any additional supply voltages. A test chip is designed and fabricated using 45-nm CMOS technology. It is achieved over 100 mV improvement for the SNM and 35 mV for the write margin. Compared to the conventional assist circuit, the cell current at the worst case condition was improved by 83%. A more stable functionality of 512-kb SRAM macros with 0.245 and 0. 327 μm2 is observed. The minimum operating voltage in the process- and temperature-worst case condition is improved by 170 mV, and its variation to 60 mV, confirming a high immunity against process and temperature variations with less than 10% area overhead. In Sect. 5.3, an array boost technique is demonstrated for low-voltage operation. The technique enhances stability of SRAM memory cells. Section 5.4 introduces design techniques of dual-port SRAM cell array, which is often used in recent SOC as data memory for graphics engines. The electrical stability of the dual-port SRAM must be considered more seriously than the single port memory. Thereby, a new array design technique for a synchronous DP-SRAM was demonstrated. Using 65-nm CMOS technology, 32-kB DP-SRAM macros were designed and subsequently fabricated. This process yielded the smallest 8T DP-cell and the highest bit density ever reported in the 65-nm era. Test results show that the speed penalty was negligible; standby leakage was reduced by 27% because of the small cell size.