Low-power and real-time address translation through arithmetic operations for virtual memory support in embedded systems

Abstract

An arithmetic-based address translation technique is presented for low-power and real-time embedded processors with virtual memory support. General-purpose virtual memory support comes with its disadvantages of excessive power consumption and nondeterministic execution times, which are the main reasons for not adopting virtual memory in energy-efficient and real-time embedded systems. To address these issues, an application-driven address translation is proposed, where most of the address translations, which are traditionally performed as translation lookaside buffer (TLB) lookups, are replaced with fast and energy-efficient addition operations. To achieve this, a program and system-wide information is used to identify sequences of consecutive virtual page numbers, which are mapped to sequences of consecutive physical page frames. For such pairs of page sequences, only the addition of a constant to the virtual page number is needed to produce the physical page frame. The proposed methodology relies on the combined efforts of compiler, operating system, and hardware architecture to achieve a significant power reduction. As the approach fundamentally eliminates conflicts inherent in the hardware translation table, execution time is not only improved but also made predictable for a large number of memory reference instructions. Experiments show power reductions in the range of 80–95% compared to a general-purpose TLB.