Low-power and low-voltage bandpass filter design for wireless receiver applications

Abstract

Low-power wireless communication chips for wearable consumer products and med-ical devices in the Internet of Things (IoT) have limited energy sources due to their sizes and placement. For this reason, there is a continuous need to reduce the power consumption of integrated circuits within such devices in order to prolong battery life and to allow operation with harvested energy. However, the lowering of on-chip supply voltage levels and bias currents for analog circuits leads to restricted performance and increased distortion of signals. In low-power receivers with reduced supply voltages, one of the blocks that severely suffers from linear range limitations is the baseband filter because the input signal has already been amplified by the radio frequency front-end circuits, and hence the baseband filter must be able to process the signal while creating minimal distortion and maximizing the output voltage swing. This thesis introduces a complex bandpass filter design technique with a large-signal linearization method to reduce distortion levels for low-power applications. A novel adaptive biasing circuit is proposed to extend the linear range of filters. A prototype first-order filter was designed in 130nm CMOS technology with a power consumption of 26.1 µW from a 0.6 V supply. The simulated center frequency and bandwidth of the filter are 2 MHz and 600 KHz, respectively. It has a simulated image rejection ratio of 22.0 dB per pole and an out-of-band spurious-free dynamic range of 56.0 dB. Compared to previous designs with low supply voltages, the adaptive biasing circuit results in a filter with lower power consumption and noise. To demonstrate the feasibility of the design methods for current wireless standards, a second-order complex filter was designed in 130nm CMOS technology, fabricated, and tested. Measurements of the complete 2nd-order filter with a center frequency at 2 MHz reveal an in-band SFDR of 47.5 dB, out-of-band SFDR of 44.7 dB, and IIP3 of -24.7 dBm. The total power consumption of the filter is 72 µW with a supply voltage of 0.6 V. The gain measurements were influenced by the loading effect from a buffer on the prototype printed circuit board, resulting in attenuation. A de-embedding process was utilized to assess this attenuation in order to obtain estimates for the filter's voltage gain (38.5 dB) and image rejection ratio (29.9 dB).