Low-power accessless SRAM macro in logic CMOS technology

Abstract

In this paper, a novel low-power SRAM based on 4-transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. A 1.8 V SRAM test chip has been fabricated in a 0.18 µm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30 % reduction in read power and 42 % reduction in write power compared to the conventional 6-transistor (6T) SRAM.