Low-Loss Continuous True Time Delay with Delay Summing

Abstract

This paper presents a delay sum true time delay (TTD) architecture. The proposed TTD divides the input signal to two signals with different time delays, then combines them in-phase at the output port. The variable time delay can be achieved by changing the power dividing and combining ratio of the two signals. The proposed TTD can provide lower insertion loss than varactor-loaded transmission line or switched delay line TTD, since it can achieve the large and continuously controlled time delay with a compact size. Also, this paper proposes a variable power divider/combiner with an increased range of the power dividing/combining ratio. The proposed delay sum TTD is demonstrated at 2.4 GHz. The measured insertion loss is only 2.3±0.25 dB with the continuously tunable delay of 843 ps (>720°), while maintaining the impedance matching below -10dB.