Low-loss and robust DWDM Echelle grating (de-)multiplexers in SOI technology

Abstract

Driven by the increasing demands of ultra-broad bandwidth transmission in telecommunications as well as in large-scale scientific experiments, interests in developing on-chip DWDM networks based on silicon photonics is increasing rapidly. With compact structures, low loss and robust fabrication, Echelle grating (EG) (de-)multiplexers become one of the key components. Two competitive design methods are the Rowland circle (RC) and the two stigmatic points (TSP) method, with the latter one offering remarkable advantages on optical aberrations and degrees of freedom. We demonstrate a self-developed design kit for both methods involving MATLAB calculation, COMSOL Multiphysics simulation and GDSII layout. In our kit, several parameters are reserved to optimize the geometry in terms of device footprint, reflector configurations etc.. By making rigorous simulation on an HPC cluster, we obtained well-performing, robust and compact EG (de-)multiplexers based on the two stigmatic points method. For the 7-channel, 9th diffraction order and 800 GHz channel spacing device, we get a simulated average optical loss of 2.3 dB and a crosstalk of less than -20 dB with an on-chip footprint of 400×690 μm2. Our silicon-photonic devices were fabricated on a 250 nm silicon-on-insulator (SOI) platform using e-beam lithography and dry etching. The comparison between measurement results of fabricated devices and simulation results was carried out, as well as a comparison between designs based on both design methods. Additionally, the experimental result of a 25- channel (de-)multiplexer with 200 GHz channel spacing in the C-band is presented to study the performance of the TSP method for a narrow channel spacing and large footprint design.