Low-Latency Radix-4 Multiplication Algorithm over Finite Fields

Abstract

The multiplication over finite fields is the most basic and important arithmetic operation. In this paper, we propose a low-latency radix-4 multiplication algorithm based shifted polynomial basis (SPB) over finite fields. The existing multiplication algorithm using SPB has the critical path delay of one 2-input AND gate, one 2-input XOR gate, and one 1-bit latch, and the latency of about 0.5 m clock cycles. Our proposed radix-4 multiplication algorithm has the critical path delay of two 2-input AND gate, two 2-input XOR gate, and one 1-bit latch, and the latency of 0.25 m clock cycles. Our radix-4 multiplication algorithm saves about 20% time complexity as compared to the existing multiplication algorithm based on SPB. Therefore, we expect that the proposed algorithm can lead to a hardware architecture which has a considerably low latency. The multiplier applying the proposed algorithm will be a highly modular architecture and be thus well suited for VLSI implementations.