Low-K Flip Chip Board Level Reliability on 65nm Technology

Abstract

Higher coefficient of thermal expansion (CTE) of printed wiring board (PWB), compared with that of silicon chip, makes the impact on thermally induced stress in IC chip by PWB a great concern for IC with Low-K inter-metal-dielectric (IMD) product reliability. To characterize and validate the 65 nm technology flip-chip (FC) package reliability, 20times20 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> test chip were assembled in a 42.5times42.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> flip-chip packages for board level reliability tests, mainly temperature cycling test, mechanical bending test and mechanical shock/vibration tests. The test results showed that no Low-K and bump joint failure was found in shock/vibration test. For bending test, flip-chip bump joint open occurred after package ball joint failure and this result implied no Low-K IC concern for product bending test. In temperature cycling test, eutectic bump FC package showed no failure during 6000 cycles test, but high lead bump FC package was found bump joint crack failure started from 1267 cycles. No Low-K failure was found for both eutectic and high lead bump FC. The board level reliability results validated 65 nm IC reliability performance. The high lead bump crack issue is under further investigation by FC package process and underfill material optimization.