Low-k Dielectrics

Abstract

As CMOS transistors were scaled, interconnects to link them are also shrunk to reduce the line pitches [1–10]. As shown in Fig. 22.1, the interconnect pitches have been shrunk from 180 nm, 140 nm, and 100 nm for 65 [4], 45 [32], and 32 nm nodes [10] LSIs, respectively. To eliminate the interconnect parasitic capacitance, low-k dielectric films which have lower permittivity than the conventional silica (SiO2) dielectrics have been introduced. Figure 22.2 shows the technology trend of the k-value and the deposition process, in which the low-k films are deposited by spin-on-dielectric (SOD) method or plasma-enhanced CVD. In the case of SOD, precursor solution is poured on a rotated wafer, and the precursor film is heated to vaporize the solvent followed by reaction and densification to make a low-k film. In the case of PECVD [36, 42], on the other hand, precursor solution is vaporized with inert carrier gas such as He, and the precursor gas is introduced into PECVD chamber with RF power. The vaporized precursor gas is exited from plasma, depositing a low-k film on a wafer heated in high vacuum. The SOD method is advantageous to decrease the k-value, while PECVD method is superior in the adhesion strength due to the possibility of in-suite plasma surface treatment in vacuum just before the low-k deposition.