Low-Cost Low-Power Self-Test Design and Verification of On-Chip ADC for System-on-a-Chip Applications

Abstract

This paper presents a low-cost low-power self-test design and verification of on-chip analog-to-digital converter (ADC) for System-on-a-Chip (SoC) applications. A methodology for performing mixed-mode built-in self-test (BIST) simulation was performed along with the BIST architecture. The architecture presented allows for generation of analog test signals of frequency up to 600 MHz, using a 4-b 2.5 Gsamples/s current steering digital-to-analog converter (DAC). Both integral nonlinearity (INL) and differential nonlinearity (DNL ) errors of test signals were obtained about 0.5 LSB by the sine wave histogram testing. The measured power dissipation for generated test signals of 600 MHz at the power supply of 1.2 V is about 5.32 mW. The current steering DAC achieves 22.3 dB of spur free dynamic range (SFDR) for 600 MHz signals.