Low-cost Hardware Architecture for Integral Image Generation using Word Length Reduction

Abstract

An integral image is widely used in face detection to calculate feature values at high speed. However, implementing integral images in hardware requires considerable logic and memory resources. This paper proposes a hardware architecture for integral image generation with reduced resource usage by applying the word length reduction method. When implemented in an FPGA, the proposed architecture uses about 83% fewer Slice LUTs than the conventional integral image method. Therefore, the proposed architecture is suitable for low-cost realtime face detection systems.