Low-cost and Real-time Hardware Implementation of Stereo Vision System on FPGA

Abstract

In this work, one of local stereo vision algorithms named SAD approach, which is used in image depth estimation, has been surveyed, and an efficient and real-time new hardware implementation has been proposed. The proposed method has been verified and tested using C implementation. The acceptable simulation results along with the detailed explanation of numerous pre-processing steps are also presented. Our innovations could be divided into two sections: architecture and algorithm. In architecture section, by using a specific architecture, memory access has been lowered and therefore, speed has been increased. In algorithm section, a part of local algorithm, known as refinement, has been substituted with a simpler and more efficient algorithm. Cyclone IV has been utilized as our hardware platform. In this article, this point would demonstrate how to use an exact but less complicated controller, which results in less area, and how to use pipeline architecture and remove repetitive and redundant memory accesses, which conduct our stereo vision system to meet the real-time constraints. Suggested hardware implementation could reach to 53fps processing speed with 100MHz clock. No processing IP core has been used. In comparison with related work, our proposed method is more efficient in logic elements usage, and accordingly in power consumption.