Low-Complexity Architectures for Parallel Long BCH Encoders

Abstract

Long BCH codes are broadly used in digital communication systems and memory storage, and parallel encoders are needed to achieve high throughput. A three-step approach can be used to eliminate the fanout bottleneck in parallel long BCH encoders achieved through unfolding, and further modifications have been developed to reduce the iteration bound. However, previous designs have high complexity, and the complexity also increases rapidly with the parallelism. In this paper, a novel encoding scheme is proposed to transform the computation so that the iteration bound of the third step can be reduced to an arbitrary value with low complexity. Besides, the proposed scheme requires low overhead to achieve higher parallelism and/or further apply the look-ahead scheme to reduce the iteration bound of the second step and hence the overall encoder. For (8191, 7684) BCH encoders with higher parallelisms, the proposed design achieves more than 50% area saving and 10% iteration bound reduction compared to the best existing design.