Low voltage stress-induced leakage current in 1.4–2.1 nm SiON and HfSiON gate dielectric layers

Abstract

This work examines stress-induced leakage current (SILC) in both ultrathin silicon oxynitride and hafnium silicate dielectric layers for future MOS technology nodes. SILC is confirmed to be sense voltage dependent and is observed to have a dependence on bulk oxide traps for both dielectric layers. A possible explanation for the sense voltage dependence is provided. SILC is found to be a greater problem in the HfSiON layers, because of its magnitude relative to the initial current. This results in the leakage current density quickly becoming greater than that for SiON. The SILC is found to have a transient component in the HfSiON layers, indicating the presence of slow electron traps. Finally, the correlation between SILC and drive current reduction is demonstrated. It is concluded that in the high-k layers investigated in this study, SILC seems more of a problem than dielectric breakdown.