Abstract
It has been shown that the low voltage gate current in ultrathin oxide metal–oxide–semiconductor devices is very sensitive to electrical stresses. Therefore, it can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements to be used. In this work, we present a study on n-MOSCAP devices at negative gate bias in the direct tunneling (DT) regime. If the low voltage stress-induced leakage current (LVSILC) depends strongly on the low sense voltages, it also depends strongly on the stress voltage magnitude. We show that two LVSILC peaks appear as a function of the sense voltage in the LVSILC region and that their magnitude, one compared to the other, depends strongly on the stress voltage magnitude. One is larger than the other at low stress voltage and smaller at high stress voltage. From our experimental results, different conduction mechanisms are analyzed. To explain LVSILC variations, we propose a model of the conduction through the ultrathin gate oxide based on two distinctly different trap-assisted tunneling mechanisms: inelastic of gate electron (INE) and trap-assisted electron (ETAT).
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.