Abstract
Approaches to the development of low-voltage low-power-demand arithmetic units on the basis of silicon-on-insulator nanotransistors are considered. The characteristics of physical models of one- and eight-bit adders based on fully depleted silicon-on-insulator complementary metal-oxide-semiconductor nanotransistors with different topological parameters are numerically analyzed. For some selected elements, the dependences of the delay time and switching power on supply voltage below 1 V are studied for different voltages at the back gate of the transistor.
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