Low Trigger Voltage and High Turn-On Speed SCR for ESD Protection in Nanometer Technology

Abstract

As CMOS technology scales down to the nanometer technology, the thickness of the gate oxide becomes thinner and thinner, the breakdown voltage of the gate oxide reduces largely. It is imperative to reduce the trigger voltage and improve the turn-on speed of the SCR for ESD protection. In order to reduce the trigger voltage, a novel gate-coupled silicon-controlled rectifier (GCSCR) device is proposed without using an external trigger circuit. In the GCSCR structure, there is a parasitic RC sub-network which can provide a potential to make the SCR turn on. The trigger voltage of the GCSCR is lower than that of the conventional SCR device to effectively protect the interior CMOS circuits. The simulation and experimental results show that the trigger voltage of the GCSCR can be adjusted by changing the sizes of the device layout parameters and the ESD robustness of the GCSCR is same as the conventional LVTSCR. For improving the turn-on speed of the SCR, a new SCR with the variation lateral base doping (VLBD) structure (VSCR) is proposed for electrostatic discharge (ESD) protection. Through theoretical analysis, the turn-on speed of the SCR was determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors of the SCR. The VLBD structure can reduce the base transit time of the bipolar transistors to improve the turn-on speed of the SCR. The experimental and simulation results show that the turn-on time of the SCR with the VLBD structure (VSCR) is 12% less than that of the MLSCR with the traditional uniform base doping without adding extra process masks and increasing the chip area.