Low Trap Density Nonleaky SiGe Quantum Well MOS Structures:Fabrication and Characteristics

Abstract

SiGe quantum well metal-oxide-semiconductor (MOS) structures were fabricated by low pressure chemical vapor deposition of the epitaxial layers, or by molecular beam epitaxy (MBE), followed by thermal oxidation of the silicon cap layer at 1100°C. Examined were the effects of the quantum layer composition, the epitaxy technique, the pre-oxidation surface preparation, the oxidation temperature, and the annealing conditions, on the device quality and the strain relaxation. Addition of Ge to the quantum well was found to increase the interface trap density, due possibly to an increase in the lattice strain, while the addition of C resulted in a reduction of the trap density, due possibly to a decrease in the lattice strain as well as passivation of the traps at the interface by C. The interface trap density was higher in the case of MBE epi layers, perhaps, due to metal contamination of the samples by the MBE growth chamber. The lowest interface trap densities and the lowest oxide leakage current densities over a range of −2.5 to 1.0 V] were obtained in the case of rapid thermal oxidation at 1100°C, without any relaxation of the strained SiGe or SiGeC layer. © 2001 The Electrochemical Society. All rights reserved.