Low Temperature Wafer Bonding for 3D Applications

Abstract

Due to the high process temperature required for fusion bonding (e.g. ~1000°C) this process was not attractive for 3D applications. In the recent years low temperature fusion bonding processes were developed for addressing low temperature applications. A low temperature CMOS compatible fusion bonding process based on plasma activation of the substrate surfaces prior bonding was developed. The low temperature fusion bonding process was used in combination with standard thin wafer manufacturing processes in order to enable and demonstrate thin layer wafer bonding with subsequent multi-layer stacking capability. The process is compatible with the high cleanliness levels required by CMOS technology and can be used for various application scenarios involving through-silicon vias (TSV) technology.