Abstract
Transparent amorphous indium–gallium–zinc oxide thin-film transistors (TFTs) were fabricated using spin-coating technique at a low annealing temperature of 300 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}{\rm C}$</tex></formula> on the 200 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\times\,$</tex></formula> 200 mm glass substrate. Solution-processed high-dielectric zirconium oxide dielectric layer, with its amorphous structure and smooth surface, was used to reduce the TFT operating voltage. The resulting TFT was produced with a maximum process temperature of 300 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}{\rm C}$</tex> </formula> , and had a saturation mobility of 0.8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm cm}^{2}/{\rm V~s}$</tex> </formula> , an ON/OFF ratio of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$10^{4}$</tex></formula> , and a threshold voltage of 0.1 V.
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