Low-Temperature Deposition of High-Quality SiO2 Films with a Sloped Sidewall Profile for Vertical Step Coverage

Abstract

SiO2 is one of the most widely used dielectric materials in optical and electronic devices. The Josephson voltage standard (JVS) chip fabrication process has rigorous requirements for the deposition temperature and step-coverage profiles of the SiO2 insulation layer. In this study, we deposited high-quality SiO2 insulation films at 60 °C using inductively coupled plasma-chemical vapor deposition (ICP-CVD) to fulfill these requirements and fabricate JVS chips simultaneously. SiO2 films have a high density, low compressive stress, and a sloped sidewall profile over the vertical junction steps. The sidewall profiles over the vertical junction steps can be adjusted by changing the radio frequency (RF) power, ICP power, and chamber pressure. The effects of sputtering etch and sloped step coverage were enhanced when the RF power was increased. The anisotropy ratio of the deposition rate between the sidewall and the bottom of the film was lower, and the sloped step coverage effect was enhanced when the ICP power was increased, or the deposition pressure was decreased. The effects of the RF power on the stress, density, roughness, and breakdown voltage of the SiO2 films were also investigated. Despite increased compressive stress with increasing RF power, the film stress was still low and within acceptable limits in the device. The films deposited under optimized conditions exhibited improved densities in the Fourier transform infrared spectra, buffered oxide etch rate, and breakdown voltage measurements compared with the films deposited without RF power. The roughness of the film also decreased. The step-coverage profile of the insulation layer prepared under optimized conditions was enhanced in the junction and bottom electrode regions; additionally, the performance of the device was optimized. This study holds immense significance for increasing the number of junctions in future devices.