Low Temperature Cyclic Deposition/Etch (CDE) of Tensile-Strained Si:P

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Our aim was to assess the feasibility of the Low Temperature Selective Epitaxial Growth of tensile-Si:P (for Raised Sources and Drains in n-type FETs). Ideally, we would like to have high amounts of tensile strain and low resistivities in t-Si:P layers grown at 550°C, with (i) mainstream Si2H6 + PH3 gases for the non-selective deposition of t-Si:P and (ii) HCl + GeH4 for the selective etches of amorphous Si:P versus monocrystalline Si:P (to have selectivity on patterned wafers). In Ref (1), we focused on deposition in such cyclic processes. Thanks to (i) high F(PH3)/(2*F(Si2H6)) Mass-Flow Ratios (MFR), (ii) a reduction of the H2 carrier flow, from the reference value of a few tens of standard liters per minute down to 1/5th of it and (iii) a chamber pressure increase, from 20 Torr up to 90 Torr, we succeeded in dramatically increase [P]subst. and reach values as high as 7.9% in t-Si:P layers. 40 Torr was the best pressure in order to simultaneously have (i) a high substitutional P concentration (6.3%), (ii) a reasonable growth rate (5.5 nm min.-1) and (iii) a low electrical resistivity (0.41 mOhm. cm), without being hampered by a layer uniformity that would be too degraded to be of use in actual devices. Those t-Si:P layers, grown with a MFR of 0.46, were of superior crystalline quality and smooth. We have otherwise shown in Ref. (2) that it was possible, thanks to (i) a reduced H2 carrier flow, (ii) a low HCl mass-flow and (iii) a relatively high GeH4 mass-flow, to etch away mono-cristalline t-Si:P at temperatures close to 550°CWe have thus evaluated the Cyclic Deposition / Etch (CDE) of t-Si:P at 550°C. Deposition occurred at 40 Torr with Si2H6 + GeH4, while (selective) etching was conducted at 90 Torr with HCl + GeH4. Pressure was ramped up or down with a 5 Torr / s slope. 15s pure HCl etchings, also at 90 Torr, were sometimes used after HCl + GeH4 etchings to remove surface Ge atoms.We first evaluated, for 10 cycles CDE processes, the impact of the HCl + GeH4 etch duration on the t-Si:P thickness and the substitutional P concentration. The deposition time / cycle was always 60s. As expected, the t-Si:P thickness decreased more or less linearly as the HCl + GeH4 etch duration / cycle increased, from ~ 50 nm for 0s down to 20-25 nm for 60s (Fig. a). Meanwhile, the “apparent” substitutional P concentration and thus the tensile strain decreased less and less, as the HCl + GeH4 etch duration/cycle increased, when using high flows of pure HCl at the end of each cycle to get rid of excess Ge atoms (from 6.2% for 0s down to 2.0% for 60s in the most favorable configuration; Fig. b). Such a tensile strain loss was shown by SIMS to be due to (i) less and less P atoms and (ii) more and more Ge atoms being present in the Si lattice as the HCl + GeH4 etch duration/cycle increased (from 6.2% and 0% for 0s down to/up to 4.4% and 5.5% for 60s; Fig. c). The surface haze of CDE-grown layers was otherwise ~ 2 times higher than that of layers grown without etchings and the electrical resistivity slightly increased with the HCl + GeH4 etch duration/cycle (from 0.38 mOhm.cm for 0s up to 0.42 mOhm.cm for 60s).Thanks to the use of 10 cycles CDE processes with various HCl + GeH4 etch durations on bulk and SiN-covered Si substrates, we then showed that an etch selectivity of ~ 6 could be expected, for a-Si:P over t-Si:P, on patterned wafers (Fig. d). The presence of numerous nuclei on SiN-covered substrates nominally free of any bi-dimensional a-Si:P layers was evidenced by haze measurements, however, hinting at a lower effective selectivity.We then switched over to patterned SOI wafers with gates. We succeeded, with 7 cycles CDE processes, in having almost full selectivity with 60s depositions and 40s etches / cycle, respectively (Fig. e). Maybe because there was a mix of a-Si:P and t-Si:P regions on such wafers, we had almost the same deposited t-Si:P thickness / CDE cycle (4.1 – 4.2 nm) whatever the HCl + GeH4 duration / cycle in the 15s – 40s range (Fig. f). Meanwhile, there was a gradual disappearance of a-Si:P on dielectrics as that etch duration increased.[1] J.M. Hartmann and J. Kanyandekwe, J. Cryst. Growth 582, 126543 (2022).[2] J.M. Hartmann and M. Veillerot, Semicond. Sci. Technol. 35, 015015 (2020). Figure 1