Low temperature and low cost planarised aluminium interconnect for sub-half micrometre VLSI circuits

Abstract

Planarised Al interconnect structures for sub-half micrometre integrated circuits have been fabricated by a novel low temperature and low pressure sputtering deposition technique. Simultaneous high aspect ratio interconnect hole fill and metal layer planarisation were achieved with moderate heat applied to processed wafers during the Al deposition. Low via resistance (~1 Ω for 0.35 µm vias) and high via chain yield (~100%) have been obtained on the wafers processed at a wafer temperature of 380°C.