Low-Subthreshold-Slope Asymmetric Double-Gate GaAs-on-Insulator Field-Effect-Transistors on Si

Abstract

In this letter, we have demonstrated low-subthreshold-slope (SS) asymmetric double-gate (DG) GaAs-on-insulator field-effect-transistors (FETs) on Si substrates via wafer bonding and epitaxial liftoff techniques. We found that DG FETs show lower SS than single-gate FETs all over the range of the drain current. A minimum value of SS was 68 mV/decade, which is very close to the theoretical limit. In addition, the achieved SS value was a record-low among the reported GaAs transistors so far.