Low skew automated clock tree generation

Abstract

We developed an automated algorithm for clock tree generation to minimize skew while taking into account a slew constraint. The topology of the generated tree depends strictly on the location of the clock loads (sinks) and their capacitance, as well as the RC characteristics of the wiring layers used. The generated clock tree is actually routed and extracted, and detailed circuit simulation is used to measure the skew and slew rate. The new algorithm was able to produce clock trees with skews less than 3% of the clock period for a variety of industrial circuits. Such low skews means that the min-delay problem is largely eliminated since the skews are on the order of an inverter delay. Furthermore, the algorithm uses the fewest buffers needed to meet the slew rate, as well as the smallest feasible size for each buffer, enabling the clock tree power to be minimized.