Low resistivity copper interconnection layers

Abstract

This paper describes the resistivity in copper interconnection layer for high-speed logic LSIs. Resistivity increases to 7.8 /spl mu//spl Omega/-cm with decreasing of thickness to 75 nm in conventional electroplated copper layer. This increase is due to the deposition of high stress and small grain copper layer. Marked increase of the orientation ratio of Cu (111)/(200) is found in this layer. Low resistivity layer can be electroplated if initial nucleation of the electroplating can be achieved uniformly. Such uniform nucleation can be attained on low stress seed layer deposited on TaSiN barrier layer. Such seed layer can also be formed by the agglomeration after the deposition. And by the electroplating from copper hexafluorosilicate solution. Resistivity in 75 nm thick as-deposited layer decreases from 7.8 /spl mu//spl Omega/-cm in conventional process to 2.1 /spl mu//spl Omega/-cm with achieving uniform nucleation in the electroplating.