Low-Resistance Cu-Sn Electroplated–Evaporated Microbumps for 3D Chip Stacking

Abstract

Low-resistance copper-tin (Cu-Sn) microbumps, with sizes varying from 5 μm × 5 μm to 20 μm × 20 μm and formed by electroplating–evaporation bumping (EEB) technology for three-dimensional integration of large-scale integrated chips, have been evaluated for their microstructure and electrical resistance. It was inferred from x-ray diffraction data that the formation of low-resistance Cu3Sn intermetallic compound (IMC) is facilitated at higher bonding temperature. Electron probe microanalysis mapping showed that, even before bonding, Cu-Sn IMCs were formed at the interface between Cu and Sn, whereas they were sandwiched between the Cu of the upper and lower microbumps after bonding. Electron backscatter diffraction analysis revealed that the crystal orientation of Sn grains was sharply localized in the (100) orientation for physical vapor deposited (PVD) sample, while electroplated Sn film exhibited a mixed crystal orientation in all (100), (110), and (001) axes. A resistance value of ~35 mΩ per bump was obtained for Cu-Sn microbumps with area of 400 μm2, which is several times lower than the resistance value reported for Cu-Sn microbumps fabricated by a pure electroplating method. The low resistance value obtained for EEB-formed Cu-Sn microbumps after bonding is explained by (i) the reduced surface roughness for evaporated Sn, (ii) the high degree of crystal grain orientation resulting from layer-by-layer growth in the PVD Sn, despite their smaller grain size, and (iii) the absence of impurity segregation at grain boundaries.