Abstract
AbstractIn order to reduce specific contact resistance at via/interconnect interface and to avoid device degradation with Cu diffusion into dielectrics, via cleaning technology is a critical issue for a scaled down Cu multilevel metallization. Effects of cleaning processes are investigated for CHF3 plasma-etched SiO2/SiN/Cu via-structures. Effects of dilute HF (DHF) cleaning, hydrogen plasma cleaning, oxygen plasma cleaning, hexafluoroacetylacetone (H(hfac)) vapor cleaning, and vacuum anneal cleaning are investigated using an angle-resolved x-ray photoelectron spectroscopy (XPS). Cu contamination removal using dilute oxalic acid (DOA) is investigated using total reflection xray fluorescence analysis (TRXRF). Based on the results, we developed an optimized cleaning sequence which consists of a brief oxygen plasma exposure, DHF dipping, followed by exposure to H(hfac) vapors. The cleaning sequence is effective in obtaining a clean dielectric surface and an oxide-free Cu surface at via bottom. Direct-contacted via structures were fabricated by a dualdamascene process using the cleaning sequence. The specific contact resistance reduces to 20% of the reported values. We expect that the via resistance is low enough to be used in 0.13 µm generation and beyond.
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