Abstract
High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.
Highlights
With an increased demand for electronics products nowadays, the complexity of chip design in high-end electronics systems has increased
To integrate many circuits with different functions into a single chip, the system-on-chip (SoC) implementation method is widely used in modern chip design
The operating clock frequency of systems can reach the gigahertz level. Systems functioning at such high performance with complex SoC design can encounter several challenges
Summary
With an increased demand for electronics products nowadays, the complexity of chip design in high-end electronics systems has increased. In the DVFS technique, the main role of a timing monitor is to measure the specified timing-critical path delay in a digital block and provide such delay information to the frequency/voltage controller. Based on the measured delay provided by the timing monitor, the DVFS controller can adjust the operating frequency and supply voltage to reduce power consumption. [5] uses a cascading structure to improve the monitoring resolution, and takes two delay lines to lower the sensitive to supply voltage variations by choosing the suitable the width and length of each metal-oxide-semiconductor.
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