Abstract
In the present day scenario, designing a circuit with low power has become very important and challenging task. The designing of any processor for portable devices demands low power. This can be achieved by incorporating low power design strategies and rules at various stages of design. To increase the performance of portable devices, the power backup should be taken in consideration, which is extremely desirable from the users prospective. As we approaches towards the sub-micron technology the requirement of low power devices increases significantly. But at the same time leakage current and dynamic power dissipation play a vital role to diminish the performance of portable devices. This paper presents techniques to reduce the power dissipation and various methodologies to increase the speed of device. That is very beneficial for designing of future VLSI circuits.
Highlights
Today more than 95 % of VLSI chips are made out of silicon
The sources of power dissipation in CMOS circuits can be broadly divided into two types, dynamic power and static power
Dynamic power dissipation can be computed effectively if the right load capacitance estimated at the nodes and by factoring in the activity factors [2]
Summary
Today more than 95 % of VLSI chips are made out of silicon. BJT's have very high speed and when using about very high packing density, we usually used MOSFET like the DRAM chip. This is based on MOSFET technology, million transistors in a given area of integrated circuit and given area of silicon. The technology of processor clock rate has increased starting with 167 megahertz to 1,000 megahertz and most of the processors are operating in the range of gigahertz. To overcome related to power dissipation problem, many scientists and researchers have proposed from the device level to the architectural level [4]. On this paper explain various power dissipation causes of power consumption, and proposed possible solutions to minimize power dissipation in a CMOS device
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